The present invention is generally directed to control circuitry for producing timing signals for electronic circuits, and more particularly to an electronic circuit having low skew differential input buffers, one for each critical transition of the input signals, for receiving differential multi-phase input signals and producing a low skew output timing signal.
It is generally known in the electronics art that timing signals often control the functions of circuits contained within an electronic circuit system. Timing signals are produced by their own circuits and generally propagate to each circuit within the electronic circuit system to effectuate control thereof.
It is also generally known in the electronics art that in certain applications it is desirable to increase and/or decrease the frequency of timing signals incorporated in an electronic circuit system. Often, the frequency of the timing signals is doubled or tripled, and other times it is divided, such as in half. The advantages of clock doublers and the like are well known in the art.
It is further well known in the art that timing signal generation circuitry typically uses input signals received by conventional differential buffers/receivers. One common drawback of the prior art is that use of conventional differential buffers/receivers produces a high edge timing skew on the generated timing signal. This relatively high skew is attributable to the inherent skew of the differential buffer/receiver.
In particular, CMOS input buffers are typically used as the conventional differential buffers/receivers in such circuitry. CMOS differential input buffers, particularly those used to receive restricted swing signal (SSTL) or differential input signals, ordinarily have considerable skew (i.e., timing variations) produced at their output signals in response to input signals transitioning from one state to another. Often, the skew is more noticeable as a result of the low-to-high input signal transition as opposed to its high-to-low transition, or vice versa. This condition is most readily apparent when the input buffers have hysteresis in order improve noise immunity.
When clock buffers, which have different output delays from different input transitions, are used in timing signal generation circuitry, the timing signal generated is relatively accurate, but has a considerable skew in at least every occurrence of one of its transitions.
Illustrating these principles, FIG. 6 shows a conventional clock doubler circuit generally designated 100 having a first input buffer 102, a second input buffer 104 and an exclusive-or (XOR) logic gate 106. A first input clock signal CLK0 is applied to the noninverting input terminal of input buffer 102, while its complement CLK0B, or alternatively a voltage reference signal VREF, is applied to the inverting input terminal of input buffer 102. A second input clock signal CLK1, which is ninety degrees out of phase with respect to first input clock signal CLK0, is applied to the noninverting input terminal of input buffer 104. Its complement CLK1B, or alternatively the voltage reference signal VREF, is applied to the inverting input terminal of input buffer 104. The output terminals of input buffers 102, 104 are connected to the input terminals of XOR gate 106 to generate a double frequency timing signal CLK2X at the output terminal of XOR gate 106. As will be appreciated by those skilled in the art, conventional clock doubler circuit 100 does not compensate for the inherent skew present in the input buffers 102, 104 shown in FIG. 6.
FIG. 7 illustrates another conventional clock doubler circuit generally designated 200 having a first input buffer 202, a second input buffer 204, and an exclusive-or (XOR) equivalent circuit designated 206. Exclusive-or circuit 206 includes two invertors 208, 210 and three NAND gates 212, 214, 216. As shown, a first input clock signal CLK0 is applied to the noninverting input terminal of input buffer 202, while its complement CLK0B, or alternatively a voltage reference signal VREF, is applied to the inverting input terminal of input buffer 202 to generates an edge timing signal P0H at the output terminal of input buffer 202. A second input clock signal CLK1, which is ninety degrees out of phase with respect to first input clock signal CLK0, is applied to the noninverting input terminal of input buffer 204. Its complement CLK1B, or alternatively the voltage reference signal VREF, is applied to the inverting input terminal of input buffer 204 to generate an edge timing signal P1H at the output terminal of input buffer 204.
The output terminal of input buffer 202 is connected to the input terminals of inverter 208 and NAND gate 212. Similarly, the output terminal of input buffer 204 is connected to the input terminals of inverter 210 and NAND gate 214. Inverter 208 generates a signal emulating edge timing signal P0L at its output terminal, which is connected to NAND gate 214. Similarly, inverter 210 generates a signal emulating edge timing signal P1L at its output terminal, which is connected to NAND gate 212. The respective output terminals for NAND gates 212, 214 are connected to the input terminals of NAND gate 216, which generates a double frequency timing signal CLK2X at its output terminal. As will be appreciated by those skilled in the art, clock doubler circuit 200 also does not compensate for the inherent skew present in the input buffers 202, 204 shown in FIG. 7.
Accordingly, while prior art timing signal generation circuitry is suitable for certain, limited applications, the timing skew attributable to such circuitry limits performance of the electronic circuit system under control.
In light of the foregoing, it is therefore desirable to develop a timing signal generation circuit that minimizes the skew attendant to input differential buffers used in that circuit.
It is also desirable to design a timing signal generation circuit that uses multiple input differential buffers on each critical edge of the output timing signal.
It is further desirable to design a clock doubler circuit that uses two separate differential signal inputs, or a total of four clock signals, to generate a low skew double frequency output signal.
It is yet further desirable to design a circuit as previously described in which the four clock signals are produced by two identical frequency signals that are ninety degrees out of phase, along with their complement signals.
It is still further desirable to design a timing signal generation circuit that includes a buffer for each edge of the output timing signal such that the output of each buffer uses the lowest skew path of the buffer and each input-to-output path is matched.
These and other objects of the preferred form of the invention will become apparent from the following description. It will be understood, however, that a circuit could appropriate the invention claimed herein without accomplishing each and every one of these objects, including those gleaned from the following description. The appended claims, not the objects, define the subject matter of this invention. Any and all objects are derived from the preferred form of the invention, not the invention in general.
The present invention is directed to a timing signal generation circuit for generating a timing signal having a predetermined number of critical transitions from a plurality of input timing signals. The circuit includes an input differential buffer for each critical transition of the timing signal. Each buffer has first and second input terminals and an output terminal. Each buffer further has a first response between its first input terminal and its output terminal and a second response between its second input terminal and its output terminal. The first response provides a generally lower skew than the second response. In this circuit, two different ones of the input timing signals are applied to the first and second input terminals of each buffer to generate a critical edge timing signal at an output terminal of each buffer indicative of a lowest skew path for a particular one of the predetermined number of critical transitions of said timing signal. The circuit also includes a logic circuit coupled to each buffer through the respective output terminals thereof.
In a preferred form, the present invention is directed to a clock doubler circuit for generating a double frequency clock signal from first, second, third and fourth input clock signals. In this arrangement, the first and second input clock signals share a common frequency and are complements of each other, while the third and fourth input clock signals share that same common frequency and are complements of each other. Further, the first and third input clock signals are ninety degrees out of phase with respect to each other. The clock doubler circuit includes a first input differential buffer having a first buffer first input terminal, a first buffer second input terminal, and a first buffer output terminal. The first input clock signal is applied to the first buffer first input terminal and the second input clock signal is applied to the first buffer second input terminal. The clock doubler circuit further includes a second input differential buffer having a second buffer first input terminal, a second buffer second input terminal, and a second buffer output terminal. The fourth input clock signal is applied to the second buffer first input terminal and the third input clock signal is applied to the second buffer second input terminal. Still further, the clock doubler circuit includes a third input differential buffer having a third buffer first input terminal, a third buffer second input terminal, and a third buffer output terminal. The third input clock signal is applied to the third buffer first input terminal and the fourth input clock signal is applied to the third buffer second input terminal. Yet further, the clock doubler circuit includes a fourth input differential buffer having a fourth buffer first input terminal, a fourth buffer second input terminal, and a fourth buffer output terminal. The second input clock signal is applied to the fourth buffer first input terminal and the first input clock signal is applied to the fourth buffer second input terminal. Finally, the clock doubler circuit includes an exclusive-or logic circuit coupled to the first, second, third and fourth input buffers through respective ones of the first, second, third and fourth buffer output terminals.